Semiconductor memory devices may be classified into volatile memory devices that lose contents stored of a memory when power is interrupted, and non-volatile memory devices that do not lose contents stored of a memory even if power is interrupted. Recently, of the non-volatile memory devices, the use of a flash memory device is increasing. A flash memory device includes a thin tunnel oxide layer formed on a silicon substrate, a floating gate and control gate sequentially stacked with a dielectric layer interposed therebetween, and source/drain regions formed in exposed regions of the substrate. In addition, each transistor of a flash memory device is capable of storing one bit and the flash memory device performs electrical programming and erasure. Such a flash memory device has a source connecting layer, which connects sources of respective unit cells to form a source line. The source connecting layer may be formed via a metal contact method wherein contacts, formed in the sources of the respective unit cells, are connected with one another. However, the metal contact method is not appropriate for highly integrated devices when considering contact margin. Therefore, to realize high integration of devices, a common source line, which is formed as a dopant diffusion layer via a Self-Aligned-Source (SAS) process, has been frequently used in recent years.
FIG. 1 is a layout of a flash memory device which includes a device isolation layer 10, active regions 20, 22, and gate lines 30, 32. SAS masks 40, 42 are used in a SAS process. Referring to FIG. 1, the device isolation layer 10 is formed in the semiconductor substrate to define the active regions 20, 22. After defining the active regions 20, 22 and forming a floating gate pattern, control gates are formed. With relation to patterning of the control gates, a common source corresponds to a space between the neighboring control gates. Subsequently, a SAS process causes chained active source resistors.
FIGS. 2A and 2B are sectional views taken along line A-A′ of FIG. 1. As shown in FIG. 2A, the gate lines 30, 32 are formed on and/or over the device isolation layer 10 with a predetermined interval. Then, when performing a SAS process, as shown in FIG. 2B, a trench 50 is formed in the device isolation layer 10A between the neighboring gate lines 30 and 32.
FIGS. 3A and 3B are sectional views taken along line B-B′ of FIG. 1. As shown in FIG. 3A, a gate pattern is formed on and/or over the active region 22 with a predetermined interval. The gate pattern includes gate lines 30, 32 corresponding to the control gates, a dielectric layer 34, a floating gate 36, and a tunnel oxide layer 38. Next, as shown in FIG. 3B, a SAS process using the SAS masks 40, 42 is performed. In most memory cells less than 0.25 μm or 0.18 μm, shallow trench isolation (STI) technology is used. The STI technology is important to reduce a cell size in a word line (WL) direction and the SAS technology is essential to reduce a cell size in a bit line (BL) direction. Simultaneously using the two technologies, however, entails a problem of excessively increasing source resistance. In consideration of design rule shrinkage, an effort to reduce a space width has been continued. However, as the space width decreases, the source resistance increases, deteriorating programming/reading speeds and resulting in a negative effect on products.